#ifndef CONFIGS_H
#define CONFIGS_H

#pragma config PLLDIV = 1			 // 4 MHz crystal, so no need to divide it to get the 4 MHz needed by PLL
#pragma config CPUDIV = OSC3_PLL4  // sets a primary clock, Fosc, = 24 MHz (Fosc/4 = 6 MHz is needed for low speed USB), chip and timers run at Fosc/4 as well.
#pragma config USBDIV = 2			 // full speed USB gets its 48 MHz signal from PLL module (the PLL's 96 MHz output is divided by 2)
#pragma config FOSC = XTPLL_XT		 // using an external, normal speed crystal, PLL module is enabled
									 // this is XTPLL_XT because USBDIV sets if the USB module uses the PLL or not.  Thus, it would be redundant to have an
									 // option for XTPLL_XTPLL.  The first part (XTPLL) sets that the main clock is using the PLL and the second part sets
									 // what the USB would use if USBDIV = 1 (not using PLL)
#pragma config FCMEN = OFF		 	 // Fail-safe clock monitor disabled
#pragma config IESO = OFF			 // Internal/External Oscillator switchover disabled
#pragma config PWRT = OFF			 // Power-up Timer disabled
#pragma config BOR = ON				 // Brown-out reset enabled in hardware only
#pragma config BORV = 3				 // Brown-out voltage at minimum setting
#pragma config VREGEN = ON			 // USB voltage regulator enabled
#pragma config WDT = OFF			 // Watchdog timer hardware disabled, software controlled
#pragma config WDTPS = 32768		 // Watchdog timer postscale 1:32768 (max)
#pragma config MCLRE = ON			 // MCLR pin enabled, RE3 input pin disabled
#pragma config LPT1OSC = OFF		 // Low power timer 1 oscillator bit low-- timer 1 configured for higher power operation
#pragma config PBADEN = OFF			 // PORTB <4:0> pins are configured as digitial I/O on reset
#pragma config CCP2MX = ON			 // CCP2 input/output is multiplexed with RC1 (vs RB3)
#pragma config STVREN = ON			 // Stack full/underflow will cause reset
#pragma config LVP = OFF			 // Single supply ICSP disabled
#pragma config XINST = OFF			 // Instruction set extension and indexed addressing mode disabled (legacy mode)
#pragma config DEBUG = OFF			 // Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
#pragma config CP0 = OFF			 // Code protection bits-- Block 0 (000800 - 001FFFh) not code-protected
#pragma config CP1 = OFF			 // (002000 - 003FFFh)
#pragma config CP2 = OFF			 // (004000 - 004FFFh)
#pragma config CPB = OFF			 // Boot block (000000 - 0007FFh) not code-protected
#pragma config CPD = OFF			 // Data EEPROM not code-protected
#pragma config WRT0 = OFF			 // Block 0 not write-protected
#pragma config WRT1 = OFF
#pragma config WRT2 = OFF
#pragma config WRTB = OFF			 // Boot block not write-protected
#pragma config WRTC = OFF			 // Configuration register not write-protected
#pragma config WRTD = OFF			 // EEPROM not write-protected
#pragma config EBTR0 = OFF			 // Block 0 not protected from table reads executed in other blocks
#pragma config EBTR1 = OFF
#pragma config EBTR2 = OFF
#pragma config EBTRB = OFF			 // Boot block not protected from table reads exectuted in other blocks
#endif // CONFIGS_H